Digital System Design

Modules & Sub Modules

M1: Digital Design Fundamentals

  • Introduction to Logic Circuits

Logic gates, representations of digital logic, integrated circuits, levels of integration, digital logic families, CMOS circuits

  • Design Methodology and CAD tools

Design entries, design abstraction levels, computer-aided design (CAD) tools, design and CAD flow using CPLD/FPGA, hierarchical design

  • Combinational Circuits

Fundamentals of Boolean algebra, switching functions, truth tables, algebraic forms of switching functions, derivation of canonical forms, combinational circuit analysis and synthesis, Karnaugh maps, encoders, decoders, tri-state outputs, encoders, multiplexers, adders, subtractors, multipliers, comparators, ROM

  • Sequential Circuits

Metastability, flip-flops, finite state machines (FSM): Mealy model FSM, Moore model FSM, state diagram, registers, counters, state machines, synchronous design methodology, clock issues, asynchronous inputs, design hazards

  • Pipelined Design

Design optimization techniques: loop unrolling, chaining, multicycling; pipelining techniques: process pipelining, loop pipelining, functional unit pipelining, distributed controller

  • Programmable Logic Devices (PLD)

Implementation platforms, cell-based, array-based, PLA, PAL, FPGA, Altera Cyclone II architecture

  • Altera Quartus II Demo

Schematic design entry, input waveform entry, compilation, simulation, pin assignment, programming, introduction to Altera DE2

M2: Verilog HDL Design and Simulation for FPGA Implementation

  • Verilog Design for FPGA Implementation

o HDL based design flow, Verilog design and program structure, structural and behavioral programs, registers, latches, tristates, counters, adder/ subtractors, multiplier, multiply-accumulators, multiplexers, RAMs, ROMs, shift registers, state machines

o Verilog data types, concatenation, slices of vectors, parameter, hierarchical design, module instantiation, operators, concurrent statements, procedural statements, blocking vs non-blocking statements

  • Register Transfers and Sequencing

o Registers transfer operations, microoperations, register transfer structures

o Register cell design, buses

o Control unit, algorithmic state machines, and hardwired/microcode control, microprogrammed control

  • I/O core design

o LCD module

o PS/2 keyboard/mouse

o VGA controller

  • Altera Quartus II Demo

o Verilog design entry, compilation, static timing analysis

Training Days

7 days

8 days